An analog-to-digital converter (ADC) converts an applied analog input signal into a digital output signal. ADCs find application in a wide variety of communication, storage and signal processing applications. Examples of different types of ADCs known to those skilled in the art include successive approximation register (SAR) ADCs, as well as other types of ADCs in which conversion is performed in multiple stages, such as pipelined ADCs and sub-ranging ADCs.
These and other conventional ADCs typically incorporate one or more comparators. In a given such comparator, if the signals to be compared are sufficiently close to one another, a corresponding comparator latch may enter a metastable condition in which it produces invalid outputs. This type of metastability condition arising in a comparator latch can be a primary cause of glitches or other undesirable disturbances at the ADC output.
In conventional analog-to-digital converters, it is difficult to reduce these and other metastability-related output disturbances to a point where very low bit error rate (BER) is achievable. For example, conventional arrangements often have difficulty achieving BER on the order of 10−17, which can be required for implementation of certain Serializer-Deserializer (SerDes) links in communication applications.